? semiconductor components industries, llc, 2001 june, 2001 rev. 5 1 publication order number: mc14049ub/d mc14049ub hex buffers the mc14049ub hex inverter/buffer is constructed with mos pchannel and nchannel enhancement mode devices in a single monolithic structure. this complementary mos device finds primary use where low power dissipation and/or high noise immunity is desired. this device provides logiclevel conversion using only one supply voltage, v dd . the inputsignal high level (v ih ) can exceed the v dd supply voltage for logiclevel conversions. two ttl/dtl loads can be driven when the device is used as cmostottl/dtl converters (v dd = 5.0 v, v ol 0.4 v, i ol 3.2 ma). note that pins 13 and 16 are not connected internally on this device; consequently connections to these terminals will not affect circuit operation. ? high source and sink currents ? hightolow level converter ? supply voltage range = 3.0 v to 18 v ? meets jedec ub specifications ? v in can exceed v dd ? improved esd protection on all inputs maximum ratings (voltages referenced to v ss ) (note 2.) symbol parameter value unit v dd dc supply voltage range 0.5 to +18.0 v v in input voltage range (dc or transient) 0.5 to +18.0 v v out output voltage range (dc or transient) 0.5 to v dd +0.5 v i in input current (dc or transient) per pin 10 ma i out output current (dc or transient) per pin +45 ma p d power dissipation, per package (note 3.) plastic soic 825 740 mw t a ambient temperature range 55 to +125 c t stg storage temperature range 65 to +150 c t l lead temperature (8second soldering) 260 c 2. maximum ratings are those values beyond which damage to the device may occur. 3. temperature derating: all packages: see figure 4. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields referenced to the v ss pin, only. extra precautions must be taken to avoid applications of any voltage higher than the maximum rated voltages to this highimpedance circuit. for proper operation, the ranges v ss v in 18 v and v ss v out v dd are recommended. unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc14049ubcp pdip16 2000/box mc14049ubd soic16 2400/box mc14049ubdr2 soic16 2500/tape & reel 1. for ordering information on the eiaj version of the soic packages, please contact your local on semiconductor representative. marking diagrams 1 16 pdip16 p suffix case 648 mc14049ubcp awlyyww soic16 d suffix case 751b 1 16 14049u awlyww soeiaj16 f suffix case 966 1 16 mc14049ub alyw mc14049ubdt tssop16 96/rail mc14049ubdtr2 tssop16 2500/tape & reel mc14049ubf soeiaj16 see note 1. mc14049ubfel soeiaj16 see note 1. tssop16 dt suffix case 948f 14 049u alyw 1 16
mc14049ub http://onsemi.com 2 figure 1. pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 out e nc in f out f nc in d out d in e out b in a out a v dd v ss in c out c in b nc = no connection figure 2. logic diagram mc14049ub 14 15 11 9 7 5 3 12 10 6 4 2 nc = pin 13, 16 v ss = pin 8 v dd = pin 1 figure 3. circuit schematic v dd v ss mc14049ub (1/6 of circuit shown) ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) ?????????? ?????????? ???? ???? ??? ??? v dd ????? ????? 55 c ????????? ????????? 25 c ????? ????? 125 c ??? ??? ?????????? ?????????? characteristic ???? ???? symbol ??? ??? v dd vdc ??? ??? min ??? ??? max ???? ???? min ??? ??? typ (4.) ???? ???? max ??? ??? min ??? ??? max ??? ??? unit ?????????? ? ???????? ? ?????????? output voltage a0o level v in = v dd or 0 ???? ? ?? ? ???? v ol ??? ? ? ? ??? 5.0 10 15 ??? ? ? ? ??? e e e ??? ? ? ? ??? 0.05 0.05 0.05 ???? ? ?? ? ???? e e e ??? ? ? ? ??? 0 0 0 ???? ? ?? ? ???? 0.05 0.05 0.05 ??? ? ? ? ??? e e e ??? ? ? ? ??? 0.05 0.05 0.05 ??? ? ? ? ??? vdc ?????????? ? ???????? ? ? ???????? ? ?????????? a1o level v in = 0 or v dd ???? ? ?? ? ? ?? ? ???? v oh ??? ? ? ? ? ? ? ??? 5.0 10 15 ??? ? ? ? ? ? ? ??? 4.95 9.95 14.95 ??? ? ? ? ? ? ? ??? e e e ???? ? ?? ? ? ?? ? ???? 4.95 9.95 14.95 ??? ? ? ? ? ? ? ??? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? e e e ??? ? ? ? ? ? ? ??? 4.95 9.95 14.95 ??? ? ? ? ? ? ? ??? e e e ??? ? ? ? ? ? ? ??? vdc ?????????? ? ???????? ? ? ???????? ? ?????????? input voltage a0o level (v o = 4.5 vdc) (v o = 9.0 vdc) (v o = 13.5 vdc) ???? ? ?? ? ? ?? ? ???? v il ??? ? ? ? ? ? ? ??? 5.0 10 15 ??? ? ? ? ? ? ? ??? e e e ??? ? ? ? ? ? ? ??? 1.0 2.0 2.5 ???? ? ?? ? ? ?? ? ???? e e e ??? ? ? ? ? ? ? ??? 2.25 4.50 6.75 ???? ? ?? ? ? ?? ? ???? 1.0 2.0 2.5 ??? ? ? ? ? ? ? ??? e e e ??? ? ? ? ? ? ? ??? 1.0 2.0 2.5 ??? ? ? ? ? ? ? ??? vdc ?????????? ? ???????? ? ? ???????? ? ?????????? a1o level (v o = 0.5 vdc) (v o = 1.0 vdc) (v o = 1.5 vdc) ???? ? ?? ? ? ?? ? ???? v ih ??? ? ? ? ? ? ? ??? 5.0 10 15 ??? ? ? ? ? ? ? ??? 4.0 8.0 12.5 ??? ? ? ? ? ? ? ??? e e e ???? ? ?? ? ? ?? ? ???? 4.0 8.0 12.5 ??? ? ? ? ? ? ? ??? 2.75 5.50 8.25 ???? ? ?? ? ? ?? ? ???? e e e ??? ? ? ? ? ? ? ??? 4.0 8.0 12.5 ??? ? ? ? ? ? ? ??? e e e ??? ? ? ? ? ? ? ??? vdc ?????????? ? ???????? ? ? ???????? ? ?????????? output drive current (v oh = 2.5 vdc) source (v oh = 9.5 vdc) (v oh = 13.5 vdc) ???? ? ?? ? ? ?? ? ???? i oh ??? ? ? ? ? ? ? ??? 5.0 10 15 ??? ? ? ? ? ? ? ??? 1.6 1.6 4.7 ??? ? ? ? ? ? ? ??? e e e ???? ? ?? ? ? ?? ? ???? 1.25 1.3 3.75 ??? ? ? ? ? ? ? ??? 2.5 2.6 10 ???? ? ?? ? ? ?? ? ???? e e e ??? ? ? ? ? ? ? ??? 1.0 1.0 3.0 ??? ? ? ? ? ? ? ??? e e e ??? ? ? ? ? ? ? ??? madc ?????????? ? ???????? ? ? ???????? ? ?????????? (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) ???? ? ?? ? ? ?? ? ???? i ol ??? ? ? ? ? ? ? ??? 5.0 10 15 ??? ? ? ? ? ? ? ??? 3.75 10 30 ??? ? ? ? ? ? ? ??? e e e ???? ? ?? ? ? ?? ? ???? 3.2 8.0 24 ??? ? ? ? ? ? ? ??? 6.0 16 40 ???? ? ?? ? ? ?? ? ???? e e e ??? ? ? ? ? ? ? ??? 2.6 6.6 19 ??? ? ? ? ? ? ? ??? e e e ??? ? ? ? ? ? ? ??? madc ?????????? ?????????? input current ???? ???? i in ??? ??? 15 ??? ??? e ??? ??? 0.1 ???? ???? e ??? ??? 0.00001 ???? ???? 0.1 ??? ??? e ??? ??? 1.0 ??? ??? m adc ?????????? ?????????? input capacitance (v in = 0) ???? ???? c in ??? ??? e ??? ??? e ??? ??? e ???? ???? e ??? ??? 10 ???? ???? 20 ??? ??? e ??? ??? e ??? ??? pf ?????????? ? ???????? ? ?????????? quiescent current (per package) ???? ? ?? ? ???? i dd ??? ? ? ? ??? 5.0 10 15 ??? ? ? ? ??? e e e ??? ? ? ? ??? 1.0 2.0 4.0 ???? ? ?? ? ???? e e e ??? ? ? ? ??? 0.002 0.004 0.006 ???? ? ?? ? ???? 1.0 2.0 4.0 ??? ? ? ? ??? e e e ??? ? ? ? ??? 30 60 120 ??? ? ? ? ??? m adc ?????????? ? ???????? ? ? ???????? ? ? ???????? ? ?????????? total supply current (5.) (6.) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) ???? ? ?? ? ? ?? ? ? ?? ? ???? i t ??? ? ? ? ? ? ? ? ? ? ??? 5.0 10 15 ????????????????? ? ??????????????? ? ? ??????????????? ? ? ??????????????? ? ????????????????? i t = (1.8 m a/khz) f + i dd i t = (3.5 m a/khz) f + i dd i t = (5.3 m a/khz) f + i dd ??? ? ? ? ? ? ? ? ? ? ??? m adc 4. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 5. the formulas given are for the typical characteristics only at 25 c. 6. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l 50) vfk where: i t is in m a (per package), c l in pf, v = (v dd v ss ) in volts, f in khz is input frequency, and k = 0.002.
mc14049ub http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? switching characteristics (7.) (c l = 50 pf, t a = 25 c) ??????????????? ? ????????????? ? ??????????????? characteristic ????? ? ??? ? ????? symbol ???? ? ?? ? ???? v dd vdc ???? ? ?? ? ???? min ???? ? ?? ? ???? typ (8.) ???? ? ?? ? ???? max ??? ? ? ? ??? unit ??????????????? ? ????????????? ? ??????????????? output rise time t tlh = (0.8 ns/pf) c l + 60 ns t tlh = (0.3 ns/pf) c l + 35 ns t tlh = (0.27 ns/pf) c l + 26.5 ns ????? ? ??? ? ????? t tlh ???? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ???? e e e ???? ? ?? ? ???? 100 50 40 ???? ? ?? ? ???? 160 100 60 ??? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? output fall time t thl = (0.3 ns/pf) c l + 25 ns t thl = (0.12 ns/pf) c l + 14 ns t thl = (0.1 ns/pf) c l + 10 ns ????? ? ??? ? ? ??? ? ????? t thl ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ???? 40 20 15 ???? ? ?? ? ? ?? ? ???? 60 40 30 ??? ? ? ? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? propagation delay time t plh = (0.38 ns/pf) c l + 61 ns t plh = (0.20 ns/pf) c l + 30 ns t plh = (0.11 ns/pf) c l + 24.5 ns ????? ? ??? ? ? ??? ? ????? t plh ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ???? 80 40 30 ???? ? ?? ? ? ?? ? ???? 120 65 50 ??? ? ? ? ? ? ? ??? ns ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? propagation delay time t phl = (0.38 ns/pf) c l + 11 ns t phl = (0.12 ns/pf) c l + 9 ns t phl = (0.11 ns/pf) c l + 4.5 ns ????? ? ??? ? ? ??? ? ????? t phl ???? ? ?? ? ? ?? ? ???? 5.0 10 15 ???? ? ?? ? ? ?? ? ???? e e e ???? ? ?? ? ? ?? ? ???? 30 15 10 ???? ? ?? ? ? ?? ? ???? 60 30 20 ??? ? ? ? ? ? ? ??? ns 7. the formulas given are for the typical characteristics only at 25 c. 8. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. figure 4. typical voltage transfer characteristics versus temperature v out , output voltage (vdc) 18 15 10 5 18 15 10 5 v in , input voltage (vdc) v dd = 5 vdc v dd = 15 vdc 55 c +125 c v dd = 10 vdc
mc14049ub http://onsemi.com 4 figure 5. typical output source characteristics figure 6. typical output sink characteristics v dd v ss 1 8 i oh v oh v ds = v oh - v dd v dd v ss 1 8 i ol v ol v dd = v ol i oh , output source currnt (madc) i ol , output sink current (madc) -50 -40 -30 -20 -10 0 -10 -8.0 -6.0 -4.0 -2.0 0 v ds , drain-to-source voltage (vdc) v gs = 5.0 vdc v gs = 10 vdc maximum current level v gs = 15 vdc 160 120 80 40 0 0 2.0 4.0 6.0 8.0 10 v ds , drain-to-source voltage (vdc) v gs = 15 vdc v gs = 10 vdc maximum current level v gs = 5.0 vdc figure 7. ambient temperature power derating p d , maximum power dissipation (mw) per package 1200 1100 1000 900 825 800 740 700 600 500 400 300 200 100 0 175 150 125 100 75 50 25 t a , ambient temperature ( c) 175 mw (p) 120 mw (d) (p) pdip (d) soic pulse generator v dd v ss 8 1 c l v out v in 20 ns 20 ns v dd v ss v oh v ol 90% 50% 10% 90% 50% 10% t plh t tlh t thl t phl output input figure 8. switching time test circuit and waveforms
mc14049ub http://onsemi.com 5 package dimensions pdip16 p suffix plastic dip package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 soic16 d suffix plastic soic package case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
mc14049ub http://onsemi.com 6 package dimensions tssop16 dt suffix plastic tssop package case 948f01 issue o ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. section nn seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 16x ref k n n
mc14049ub http://onsemi.com 7 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z soeiaj16 f suffix plastic eiaj soic package case 96601 issue o
mc14049ub http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc14049ub/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
|
